Nitride semiconductor structure

ABSTRACT

A nitride semiconductor substrate includes an epitaxy substrate, a patterned nitride semiconductor pillar layer, a nitride semiconductor layer, and a mask layer is provided. The nitride semiconductor pillar layer includes a plurality of first patterned arranged hollow structures and a plurality of second patterned arranged hollow structures formed among the first patterned arranged hollow structures. The second patterned arranged hollow structures have nano dimensions. The nitride semiconductor pillar layer is formed on the epitaxy substrate, and the nitride semiconductor layer is formed on the nitride semiconductor pillar layer. The mask layer covers surfaces of the nitride semiconductor pillar layer and the epitaxy substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of and claims priority benefit of U.S.application Ser. No. 12/584,942, filed on Sep. 14, 2009, now allowed,which is a continuation-in-part of and claims the priority benefit ofU.S. application Ser. No. 11/554,603, filed on Oct. 31, 2006, now U.S.Pat. No. 7,772,595. The prior U.S. application Ser. No. 11/554,603claims the priority benefit of Taiwan application serial no. 95132153,filed on Aug. 31, 2006. The prior U.S. application Ser. No. 12/584,942claims the priority benefit of Taiwan application serial no. 98109394,filed on Mar. 23, 2009 and Taiwan application serial no. 98109393, filedon Mar. 23, 2009. The entirety of each of the above-mentioned patentapplications is hereby incorporated by reference herein and made a partof this specification.

BACKGROUND OF THE INVENTION

1. Technical Field

The disclosure relates to a nitride semiconductor structure and a methodfor manufacturing the same. 2. Background

In recent years, light emitting diodes (LEDs) and laser diodes (LDs) arenow prevailing in commercial use. For instance, a mixture of blue andyellow phosphor powder made of gallium nitride (GaN) is capable ofgenerating white light, which leads to high luminance and substantiallylow power consumption in comparison with a conventional light bulb. Inaddition, the LED has a lifetime of more than tens of thousand hours,longer than that of the conventional light bulb.

In the process of manufacturing a GaN semiconductor light-emittingelement, due to difference in lattice constants and thermal expansioncoefficients between a GaN semiconductor layer and an epitaxy substrate,the GaN semiconductor easily encounters the problems of threadingdislocation and thermal stresses during an epitaxy process, whichdeteriorates luminance efficiency of the light-emitting element.

According to the related art, a method of separating the GaNsemiconductor layer from the epitaxy substrate includes applying anirradiating method whereby laser beams pass through a substrate andilluminate an interlayer between the substrate and the GaN semiconductorlayer. Thus, the GaN semiconductor layer and the epitaxy substrate areseparated. Moreover, a wet etching method can also be performed todirectly remove a barrier structure between the substrate and the GaNsemiconductor layer so as to weaken a connection structure therebetweenand to further separate the GaN semiconductor layer from the epitaxysubstrate. In addition, a vapor phase etching process can be performedat a high temperature to directly remove the interlayer between the GaNsemiconductor layer and the epitaxy substrate. Thus, the GaNsemiconductor layer and the epitaxy substrate are separated.

For instance, in U.S. Pat. No. 6,582,986, a method of forming a GaNsemiconductor layer by pendeo-epitaxy is disclosed. This method isadapted for being applied to materials apt to be etched, e.g., a carbonsilicon substrate, while stresses are prone to be concentrated at abuffer layer which is located between the epitaxy substrate and the GaNsemiconductor layer and serves as a seed.

On the other hand, in PCT publication no. WO2007/107757, a method ofadjusting epitaxy parameters is provided. As indicated in FIG. 1, anepitaxy process is performed directly on an epitaxy substrate 100 toform a GaN nanocolumn 102 on a nitride layer 101. Next, by using the GaNnanocolumn 102 as a seed, an epitaxial lateral over growth (ELOG)process is performed to form a GaN semiconductor thick film 104. Acooling process is then carried out to crack an interface between theGaN semiconductor layer 104 and the epitaxy substrate 100. Thereafter, amechanical force is applied to separate a GaN thick film from the GaNsemiconductor layer 104 and the epitaxy substrate 100.

SUMMARY

In an embodiment of the disclosure, a nitride semiconductor substrateincluding an epitaxy substrate, a nitride pillar layer, a nitridesemiconductor layer, and a mask layer is provided. The nitride pillarlayer includes first patterned arranged pillars and second patternedarranged pillars. The nitride pillar layer is formed on the epitaxysubstrate. A width of a cross-section of each of the second patternedarranged pillars is smaller than a width of a cross-section of each ofthe first patterned arranged pillars, and a distance among each of thesecond patterned arranged pillars is longer than a distance among eachof the first patterned arranged pillars. Surfaces of the epitaxysubstrate, the first patterned arranged pillars, and the secondpatterned arranged pillars are covered by the mask layer. The nitridesemiconductor layer is formed on the nitride pillar layer.

In another embodiment of the disclosure, a method of manufacturing anitride semiconductor substrate is provided. In the method, a pluralityof first patterned arranged pillars are formed on a surface of anepitaxy substrate, and a mask layer covering sidewalls and parts of topsurfaces of the first patterned arranged pillars is formed on thesurface of the epitaxy substrate. Next, a plurality of second patternedarranged pillars are formed on the first patterned arranged pillars.Here, a width of a cross-section of each of the second patternedarranged pillars is smaller than a width of a cross-section of each ofthe first patterned arranged pillars, and a distance among each of thesecond patterned arranged pillars is longer than a distance among eachof the first patterned arranged pillars. An ELOG (epitaxial lateral overgrowth) process is then performed on the second patterned arrangedpillars to form a nitride semiconductor layer.

In yet another embodiment of the disclosure, a nitride semiconductorsubstrate including an epitaxy substrate, a patterned nitridesemiconductor pillar layer, a nitride semiconductor layer, and a masklayer is provided. The nitride semiconductor pillar layer includes aplurality of first patterned arranged hollow structures and a pluralityof second patterned arranged hollow structures formed among the firstpatterned arranged hollow structures. The second patterned arrangedhollow structures have nano dimensions. The nitride semiconductor pillarlayer is formed on the epitaxy substrate, and the nitride semiconductorlayer is formed on the nitride semiconductor pillar layer. The masklayer covers surfaces of the nitride semiconductor pillar layer and theepitaxy substrate.

In still another embodiment of the disclosure, a method of manufacturinga nitride semiconductor substrate is provided. In the method, apatterned nitride semiconductor pillar layer is formed on a surface ofan epitaxy substrate. The nitride semiconductor pillar layer has aplurality of first patterned arranged hollow structures and a pluralityof second patterned arranged hollow structures located among the firstpatterned arranged hollow structures. Here, the second patternedarranged hollow structures have nano dimensions. Next, a mask layer isformed on a sidewall of the nitride semiconductor pillar layer and thesurface of the epitaxy substrate. An ELOG process is then performed withuse of the nitride semiconductor pillar layer as a seed so as to formthe nitride semiconductor layer.

In order to the make aforementioned and other features and advantages ofthe disclosure more comprehensible, embodiments accompanied with figuresare described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a simplified sectional view of a conventional nitridesemiconductor substrate.

FIG. 2 is a simplified sectional view of a nitride semiconductorsubstrate according to a first embodiment of the disclosure.

FIG. 3 is a simplified sectional view of a nitride semiconductorsubstrate according to a second embodiment of the disclosure.

FIGS. 4A to 4I are sectional views illustrating a process ofmanufacturing a nitride semiconductor substrate according to a thirdembodiment of the disclosure.

FIGS. 5A to 5H are sectional views illustrating a process ofmanufacturing a nitride semiconductor substrate according to a fourthembodiment of the disclosure.

FIGS. 6A and 6B are SEM photographs respectively exhibiting a prototypesample made in accordance with the third embodiment and the fourthembodiment.

FIG. 7A is a simplified sectional view of another nitride semiconductorsubstrate according to an embodiment of the disclosure.

FIG. 7B is a schematic view illustrating that a nitride semiconductorfreestanding substrate is formed by performing a separation process onthe nitride semiconductor substrate depicted in FIG. 7A.

FIGS. 8A to 8H are sectional views illustrating a process ofmanufacturing another nitride semiconductor substrate according to anembodiment of the disclosure.

FIG. 8I is a sectional view illustrating a process of manufacturing anitride semiconductor freestanding substrate according to an embodimentof the disclosure.

DESCRIPTION OF EMBODIMENTS

FIG. 2 is a simplified sectional view of a nitride semiconductorsubstrate according to a first embodiment of the disclosure.

Referring to FIG. 2, the nitride semiconductor substrate in the firstembodiment includes an epitaxy substrate 200, a nitride pillar layer 202(containing a plurality of first patterned arranged pillars 204 and aplurality of second patterned arranged pillars 206), a nitridesemiconductor layer 208, and a mask layer 210. Here, a material of theepitaxy substrate 200 is, for example, sapphire, silicon carbide,silicon, gallium arsenide, or other substrate materials suitable forimplementing an epitaxy process. A material of the nitride pillar layer202 is, for example, a III-nitride, such as nitride of boron, aluminum,gallium, indium, thallium or combination thereof. A thermal expansioncoefficient of the epitaxy substrate 200 may be different from that ofthe nitride semiconductor layer 208. The nitride pillar layer 202 isformed on the epitaxy substrate 200, and the entire nitridesemiconductor layer 208 is formed on the nitride pillar layer 202. Themask layer 210 covers surfaces of the first pillars 204, the secondpillars 206, and the epitaxy substrate 200. Here, by performing aphotolithography and etching process, the first pillars 204 and thesecond pillars 206 can have dimensions required for performing asubsequent separation process.

Referring to the cross-sections of the first pillars 204 and the secondpillars 206 as depicted in FIG. 2, the first and the second pillars 204and 206 appear to be in a block shape, while the first pillars 204 orthe second pillars 206 can in fact have a stripe-shaped arrangement, adot-shaped arrangement, or a meshed arrangement as a whole. Further, itcan be observed from the cross-section in FIG. 2 that a hollow is formedbetween the first pillars 204 and the second pillars 206 by the masklayer 210. A width of a cross-section a2 of each of the second pillars206 is smaller than a width of a cross-section al of each of the firstpillars 204, and a distance b2 among adjacent two of the second pillars206 is greater than a distance b1 among adjacent two of the firstpillars 204. Hence, in subsequent processes, the thickness of thenitride semiconductor layer 208 is increased, and strength of thenitride semiconductor layer 208 gradually becomes sufficient. As such,when the surrounding temperature is decreased, a freestanding nitridesemiconductor substrate is automatically separated from the interface(the weakest section) between the epitaxy substrate 200 and the nitridepillar layer 202 (containing the first pillars 204 and the secondpillars 206) due to the difference in thermal expansion coefficients ofthe epitaxy substrate 200 and the nitride pillar layer 202. In otherwords, a freestanding nitride semiconductor substrate is spontaneouslyseparated from any interface between the second pillars 206 and thenitride semiconductor layer 208.

For instance, by performing the photolithography and etching process,the cross-section a1 of each of the first pillars 204, the cross-sectiona2 of each of the second pillars 206, the distance b1 among adjacent twoof the first pillars 204, and the distance b2 among adjacent two of thesecond pillars 206 can have dimensions required for performing thesubsequent separation process. To better describe the disclosure, aratio of the cross-section a1 of each of the first pillars 204 to thedistance b1 among adjacent two of the first pillars 204 and a ratio ofthe cross-section a2 of each of the second pillars 206 to the distanceb2 among adjacent two of the second pillars 206 are respectively definedas a fill factor FF. Namely, FF1=a1/b1, and FF2=a2/b2. For instance, inthe present embodiment, FF1 may be less than or equal to 1and FF2 may beless than or equal to 0.8, preferably FF1 is about 0.75 and FF2 is about0.6. The dimensions and ratios of the above-referenced components aresimply exemplary and should not be construed as limitations of thedisclosure. Person having ordinary skill in the pertinent art are ableto modify and fulfill the disclosure by applying the existingtechnology. For instance, the cross-section a1 of each of the firstpillars 204 ranges from 2.1 μm to 4.2 μm approximately, and thecross-section a2 of each of the second pillars 206 ranges from 1.3 μm to3.6 μm approximately. In addition, if the nitride pillar layer 202 andthe nitride semiconductor layer 208 are not separated, it may beaccomplished by adjusting FF1 and FF2 appropriately, for example, FF1may be more than 1; FF2 may be more than 0.8.

According to an embodiment of the disclosure, a thickness of the nitridesemiconductor layer 208 can be adjusted in the manufacturing processbased on actual demands. For example, when a thickness t3 of the nitridesemiconductor layer 208 is greater than 100 μm, a freestanding nitridesemiconductor substrate can be formed by performing a separation processon the nitride semiconductor layer 208. Alternatively, as indicated inFIG. 3 below, a thin film can be formed.

FIG. 3 is a simplified sectional view of a nitride semiconductorsubstrate according to a second embodiment of the disclosure.

Referring to FIG. 3, the nitride semiconductor substrate in the secondembodiment includes an epitaxy substrate 300, a nitride pillar layer 302(containing a plurality of first patterned arranged pillars 304 and aplurality of second patterned arranged pillars 306), a nitridesemiconductor layer 308, and a mask layer 310. Materials and dimensionsof the components described herein are identical or similar to thosediscussed in the first embodiment, while the difference therebetweenlies in that a thickness t1 of each of the second pillars 306 is equalto a thickness t2 of the mask layer 310. Hence, a contact area betweenthe nitride semiconductor layer 308 and the underlying mask layer 310 islarge, which is conducive to formation of the nitride semiconductorlayer 308 in the form of a thin film. It is likely for the nitridesemiconductor layer 308 discussed herein not to be separated from theepitaxy substrate 300. Instead, elements 312 (e.g. LEDs or Laserelements) can be directly formed on a surface of the nitridesemiconductor layer 308 in subsequent processes. Moreover, the epitaxysubstrate 300 and the nitride semiconductor layer 308 can be separatedfrom each other by applying an existing technique in the last step.

FIGS. 4A to 4I are sectional views illustrating a process ofmanufacturing a nitride semiconductor substrate according to a thirdembodiment of the disclosure.

First, a plurality of first patterned arranged pillars is formed on asurface of the epitaxy substrate 400, which is shown in FIGS. 4A to 4Baccording to the third embodiment. Referring to FIG. 4A, a materiallayer 402 is formed on the surface of the epitaxy substrate 400. Amaterial of the epitaxy substrate 400 is, for example, sapphire, siliconcarbide, silicon, gallium arsenide, or other substrate materialssuitable for implementing an epitaxy process. The material layer 402 is,for example, made of III-nitride, such as nitride of boron, aluminum,gallium, indium, thallium or combination thereof. Besides, a thicknessof the material layer 402 ranges from 3 μm to 5 μm. Next, a patternedmask 404 is formed on the material layer 402, and a portion of a surfaceof the material layer 402 is exposed. Here, the patterned mask 404 is,for example, made of silicon nitride or photoresist.

Thereafter, referring to FIG. 4B, the material layer 402 is removed byusing the patterned mask 404 as a mask, such that a plurality of firstpatterned arranged pillars 406 is formed. Here, the step of removing thematerial layer 402 can include removing a portion of the epitaxysubstrate 400. After that, if it is deemed necessary, a plurality ofregular or irregular nano-scale pillar structures can be formed byperforming an etching process on the first pillars 406. This isconducive to release of material stresses and further reduction ofdislocation density.

Afterwards, in order to form a mask layer on the surface of the epitaxysubstrate 400, the process depicted in FIGS. 4C to 4G is performed inthe third embodiment. Referring to FIG. 4C, the patterned mask 404depicted in FIG. 4B is etched to reduce a width of the patterned mask404, such that a patterned mask 404 a having a width W1 is formed. Here,parts of top surfaces 406 a of the first pillars 406 which are notcovered by the patterned mask 404 a are exposed.

Next, referring to FIG. 4D, a thin film 408 is formed to entirely coverthe patterned mask 404 a, the first pillars 406, and a portion of thesurface of the epitaxy substrate 400. The thin film 408 is, for example,made of silicon nitride, silicon oxide, metal tungsten, and so forth.

Thereafter, referring to FIG. 4E, in order to remove the thin film 408on the patterned mask 404 a, a photoresist layer 410 can be formed toentirely cover the thin film 408.

Referring to FIG. 4F, the photoresist layer 410 is then etched to exposethe thin film 408 on a top surface 404 b of the patterned mask 404 a.The exposed thin film 408 is then removed by using the photoresist layer410 as a mask, such that the top surface 404 b of the patterned mask 404a is exposed.

After that, referring to FIG. 4G, the patterned mask 404 a and thephotoresist layer 410 depicted in FIG. 4F are removed to expose parts ofthe top surfaces 406 a of the first pillars 406. Thereby, a mask layer412 covering the surface of the epitaxy substrate 400 and sidewalls andparts of the top surfaces 406 a of the first pillars 406 is formed.

Next, referring to FIG. 4H, a plurality of second patterned arrangedpillars 414 is epitaxially grown from parts of the top surfaces 406 a ofthe first pillars 406. Here, a radius of each of the second pillars 414is shorter than a width of a cross-section of each of the first pillars406, and a distance among adjacent two of the second pillars 414 isgreater than a distance among adjacent two of the first pillars 406.Here, a method of epitaxially growing the second pillars 414 is, forexample, a hydride vapor-phase epitaxy (HVPE) method, a metal organicvapor-phase epitaxy (MOVPE) method, or a molecular beam epitaxy (MBE)method. The second pillars 414 are, for example, made of III-nitride,such as nitride of boron, aluminum, gallium, indium, thallium orcombination thereof. Preferably, the second pillars 414 and the firstpillars 406 are made of the same material. The cross-sections of thefirst pillars 406 and the second pillars 414 are shown, and thereforethe first and the second pillars 406 and 414 appear to have a blockshape. However, the first pillars 406 or the second pillars 414 can infact have a stripe-shaped arrangement, a dot-shaped arrangement, or ameshed arrangement as a whole. An ELOG process is then performed on thesecond pillars 414 to form a nitride semiconductor layer 416 made ofgallium nitride (GaN), aluminum nitride (AlN), gallium indium nitride(GaInN), aluminum gallium nitride (AlGaN), or aluminum gallium indiumnitride (AlGaInN), for example. The ELOG process is, for example, anHVPE process, an MOVPE process, or an MBE process.

Finally, referring to FIG. 4I, when a thickness of the nitridesemiconductor layer 416 is equal to or greater than 100 μm, a coolingprocess can be selectively performed to separate the nitridesemiconductor layer 416 from the surface of the epitaxy substrate 400 asindicated in FIG. 4I. Owing to shear stresses which are caused by adifference in thermal expansion coefficients of the epitaxy materials,an interface which is located between the second pillars 414 and thenitride semiconductor layer 416 and has a weak structural strength isautomatically cracked.

In addition to the fabrication process described in the thirdembodiment, other fabrication processes can be carried out in thedisclosure as discussed in the next embodiment.

FIGS. 5A to 5H are sectional views illustrating a process ofmanufacturing a nitride semiconductor substrate according to a fourthembodiment of the disclosure.

First, a plurality of first patterned arranged pillars is formed on asurface of a epitaxy substrate 500, which is shown in FIGS. 5A to 5Daccording to the fourth embodiment. Referring to FIG. 5A, a materiallayer 502 and a separation layer 504 are sequentially formed on thesurface of the epitaxy substrate 500. Here, the material layer 502 is,for example, made of III-nitride, such as nitride of boron, aluminum,gallium, indium, thallium or combination thereof. A thickness of thematerial layer 502 ranges from 3 μm to 5 μm, for example. Besides, theseparation layer 504 can be made of a material suitable for beingwet-etched, such as metal oxide (e.g. indium tin oxide), and a thicknessof the separation layer 504 ranges from 100 nm to 200 nm, for example.

Next, referring to FIG. 5B, a patterned mask 506 is formed on theseparation layer 504, and a portion of a surface of the separation layer504 is exposed. Here, the patterned mask 506 is, for example, made ofsilicon nitride or photoresist.

Thereafter, referring to FIG. 5C, the separation layer 504 is removed byusing the patterned mask 506 as a mask. Further, the separation layer504 is etched to reduce a width thereof, such that a patternedseparation layer 504 a having a width W2 is formed. Here, the width W2of the patterned separation layer 504 a is less than a width W3 of thepatterned mask 506.

After that, referring to FIG. 5D, the material layer 502 illustrated inFIG. 5C is removed by using the patterned mask 506 as the mask, suchthat a plurality of first patterned arranged pillars 508 is formed. Amethod of removing the material layer 502 is, for example, ananisotropic etching method. Moreover, in the step of removing thematerial layer 502, a portion of the epitaxy substrate 500 can also beremoved to ensure that the first pillars 508 are not connected to oneanother.

Next, in order to form a mask layer on the surface of the epitaxysubstrate 500, referring to FIGS. 5E to 5F, a thin film 510 is formed toentirely cover the patterned mask 506, the separation layer 504 a, thefirst pillars 508, and a portion of the surface of the epitaxy substrate500. The thin film 510 is, for example, made of silicon nitride, siliconoxide, metal tungsten, and so forth.

As shown in FIG. 5F, the separation layer 504 a is then removed to peeloff the patterned mask 506 and a portion of the thin film 510, such thata mask layer 512 is formed, and that parts of top surfaces 508 a of thefirst pillars 508 are exposed.

Afterwards, referring to FIG. 5G, a plurality of second patternedarranged pillars 514 is epitaxially grown from parts of the top surfaces508 a of the first pillars 508 by conducting an HVPE method, an MOVPEmethod, or an MBE method, for example. The second pillars 514 are, forexample, made of nitride, such as gallium nitride, aluminum nitride,aluminum gallium nitride, and so on. Preferably, the second pillars 514and the first pillars 508 are made of the same material. An ELOG processis then performed on the second pillars 514 to form a nitridesemiconductor layer 516. Here, the ELOG process is, for example, an HVPEprocess, an MOVPE process, or an MBE process. The nitride semiconductorlayer 516 is, for example, made of gallium nitride, aluminum nitride,gallium indium nitride, aluminum gallium nitride, or aluminum galliumindium nitride.

Finally, referring to FIG. 5H, the nitride semiconductor layer 516formed in the fourth embodiment is adapted for forming a thin film, andit is possible for the nitride semiconductor layer 516 not to beseparated from the hetero-substrate 500 and for the subsequent formationof elements 518 (e.g. LEDs or Laser elements). Moreover, other than thepossibility that the nitride semiconductor layer 516 is not separatedfrom the hetero-substrate 500, it is also likely for the nitridesemiconductor layer 516 and the hetero-substrate 500 not to be separatedfrom each other by applying an existing technique in the last step.

The finished structure may be separated or not in the first (or third)embodiment or the second (or fourth) embodiment theoretically. Thedeterminant whether the finished structure is separated or not is atleast one design of FF1, FF2 and the thickness of the nitridesemiconductor layer. Therefore, the person having ordinary skill in theper can modify the parameters with regard to at least one design of FF1,FF2 and the thickness of the nitride semiconductor layer in order tofulfill the need of actual process, and no further description isprovided herein.

FIGS. 6A and 6B are SEM photographs respectively exhibiting a prototypesample made in accordance with the third embodiment and the fourthembodiment. Here, FIG. 6A is the SEM photograph substantially showingmanufacturing steps up to those depicted in FIG. 4G according to thethird embodiment, while FIG. 6B is the SEM photograph substantiallyshowing manufacturing steps up to those depicted in FIG. 5F according tothe fourth embodiment.

FIG. 7A is a simplified sectional view of a nitride semiconductorsubstrate according to another embodiment of the disclosure.

Referring to FIG. 7A, the nitride semiconductor substrate 700 includesan epitaxy substrate 702, a patterned nitride semiconductor pillar layer704, a nitride semiconductor layer 706, and a mask layer 708. Thenitride semiconductor pillar layer 704 is formed by a plurality of firstpatterned arranged hollow structures 710 and a plurality of secondpatterned arranged hollow structures 712, and the second hollowstructures 712 have nano dimensions. For instance, a height and a widthof the second hollow structures 712 respectively range from 1 μm to 5 μmand from 30 nm to 500 nm, for example. Besides, a height of the firsthollow structures 710 ranges from 1 μto 10 μm, for example. Thedimensions and ratios disclosed herein are simply exemplary and shouldnot be construed as limitations of the disclosure. People havingordinary skill in the art are able to modify and fulfill the disclosureby applying the existing technology. On the other hand, when observedfrom the cross-section, the first hollow structures 710 are cyclicallyarranged, while the second hollow structures 712 are regularly arrangedor randomly arranged. Additionally, the first hollow structures 710 canhave a stripe-shaped arrangement, a dot-shaped arrangement, or a meshedarrangement as a whole.

Here, a material of the epitaxy substrate 702 is, for example, sapphire,silicon carbide, silicon, gallium arsenide, or other substrate materialssuitable for implementing an epitaxy process. The nitride semiconductorpillar layer 704 is, for example, made of a III-nitride, such as nitrideof boron, aluminum, gallium, indium, thallium or combination thereof.The nitride semiconductor pillar layer 704 is formed on the epitaxysubstrate 702, and the entire nitride semiconductor layer 706 is formedon the nitride semiconductor pillar layer 704. The mask layer 708 coverssurfaces of the nitride semiconductor pillar layer 704 and the epitaxysubstrate 702. A material of the mask layer 708 can be a dielectricmaterial, such as silicon oxide or silicon nitride.

Further, by modifying the fabrication process upon actual demands, thenitride semiconductor layer 706 can be in the form of a thick film or athin film. For instance, when a thickness of the nitride semiconductorlayer 706 is greater than 50 μm, a freestanding nitride semiconductorsubstrate can be formed by performing a separation process 714 on thenitride semiconductor layer 706. Here, the freestanding nitridesemiconductor substrate includes the nitride semiconductor layer 706,the nitride semiconductor pillar layer 704, and the mask layer 708 onthe surface of the nitride semiconductor pillar layer 704, as indicatedin FIG. 7B.

Likewise, by performing a photolithography and etching process, adistance a3 among each of the first hollow structures 710 and a width ofeach of the first hollow structures can have dimensions required forimplementing the separation process 714, and a height h and a width b3of each of the second hollow structures 712 can have an irregular nanodimension. To better describe the disclosure, a ratio of the distance a3to the width a4 of the first hollow structures 710 is defined as afiller factor FF. Namely, FF=a3/a4. For instance, in the presentembodiment, FF≦2 (e.g. FF=1), and the height h of the second hollowstructures 712 can be 1 μm. The dimensions and ratios disclosed hereinare simply exemplary and should not be construed as limitations of thedisclosure. People having ordinary skill in the pertinent art are ableto modify and fulfill the disclosure by applying the existingtechnology. For example, the distance a3 ranges from 1 μm to 10 μm(preferably from 1 μm to 5 μm), and the width b3 ranges from 30 nm to500 nm (preferably from 30 nm˜300 nm).

Referring to FIG. 7B, in subsequent processes, the thickness of thenitride semiconductor layer 706 is increased, and strength of thenitride semiconductor layer 706 gradually becomes sufficient. As such,when the surrounding temperature is decreased down to the roomtemperature, a freestanding nitride semiconductor substrate isautomatically separated from the interface (the weakest section) betweenthe epitaxy substrate 702 and the nitride semiconductor pillar layer 704due to the difference in thermal expansion coefficients of the epitaxysubstrate 702 and the nitride semiconductor pillar layer 704. In otherwords, a freestanding nitride semiconductor substrate is spontaneouslyseparated from an interface between the epitaxy substrate 702 and thepatterned nitride semiconductor pillar layer 704.

In addition, given that the nitride semiconductor layer 706 is in a formof a thin film (e.g. a thickness of the nitride semiconductor layer 706is less than 50 μm), the nitride semiconductor substrate 700 depicted inFIG. 7A can serve as a nitride template. Similarly, through properlysetting the FF value and the height h, e.g., FF≧0.5 and h≦5 μm, thedislocation density can be reduced, and the nitride semiconductor layer706 is thus not cracked.

FIGS. 8A to 8H are sectional views illustrating a process ofmanufacturing another nitride semiconductor substrate according to anembodiment of the disclosure.

First, referring to FIG. 8A, a nitride semiconductor material layer 802is formed on a surface of an epitaxy substrate 800. A material of theepitaxy substrate 800 is, for example, sapphire, silicon carbide,silicon, gallium arsenide, or other substrate materials suitable forimplementing an epitaxy process. The nitride semiconductor materiallayer 802 is, for example, made of a III-nitride, such as nitride ofboron, aluminum, gallium, indium, thallium or combination thereof. Athickness of the nitride semiconductor material layer 802 ranges from 1μm to 10 μm, for example. Additionally, a method of forming the nitridesemiconductor material layer 802 on the surface of the epitaxy substrate800 is, for example, an HVPE method, an MOVPE method, or an MBE method.Next, a photoresist layer 804 is formed on the nitride semiconductormaterial layer 802.

Thereafter, referring to FIG. 8B, by applying a photolithographytechnique or the like, the photoresist layer 804 is developed, and apatterned photoresist layer 804 a exposing a portion of a surface of thenitride semiconductor material layer 802 is formed. After that, thenitride semiconductor material layer 802 is removed by performing areactive ion etching (RIE) process or an inductive coupling plasma (ICP)etching process with use of the patterned photoresist layer 804 a as amask, such that a nitride semiconductor pattern layer 806 is formed.Besides, a portion of the epitaxy substrate 800 can also be removed inthe step of removing the nitride semiconductor material layer 802.

Afterwards, referring to FIG. 8C, the patterned photoresist layer 804 ais removed (as shown in FIG. 8B), and a sacrificial mask layer 808 isformed on surfaces of the nitride semiconductor pattern layer 806 andthe epitaxy substrate 800. The sacrificial mask layer 808 covers thesurface of the nitride semiconductor pattern layer 806. Here, thesacrificial mask layer 808 can be made of a dielectric material, such assilicon oxide or silicon nitride.

Referring to FIG. 8D, a metal thin film 810 is then formed on a surfaceof the sacrificial mask layer 808 but is not formed on sidewalls of thesacrificial mask layer 808. In the present embodiment, the metal thinfilm 810 is metal nickel, for example.

Next, referring to FIG. 8E, a high temperature annealing process isperformed at 850° C., for example. Thereby, the metal thin film 810 isautomatically transformed into a plurality of ball-shaped metalsaggregated together due to surface tension difference in materials. Aradius of each of the ball-shaped metals ranges from 30 nm to 500 nm,for example. Besides, a patterned mask layer 812 (the ball-shapedmetals) is formed on the surface of the sacrificial mask layer 808, andthe patterned mask layer 812 has nano-sized patterns.

Afterwards, referring to FIG. 8F, the sacrificial mask layer 808 and thenitride semiconductor pattern layer 806 are etched by performing ananisotropic etching process (e.g., an RIE process or an ICP etchingprocess) with use of the patterned mask layer 812 as a mask. Thereby, anitride semiconductor pillar layer 806 a containing a plurality of thirdpatterned arranged hollow structures 814 and a plurality of fourthpatterned arranged hollow structures 816 is formed. The nitridesemiconductor pillar layer 806 a is, for example, made of galliumnitride, aluminum nitride, aluminum gallium nitride, indium nitride,indium gallium nitride, or aluminum gallium indium nitride. Thesacrificial mask layer 808 and the patterned mask layer 812 are thenremoved.

Thereafter, referring to FIG. 8G, a mask layer 818 is formed onsidewalls of the nitride semiconductor pillar layer 806 a and on thesurface of the epitaxy substrate 800. For instance, the mask layer 818can be formed by first forming a dielectric thin film entirely coveringthe surfaces of the nitride semiconductor pillar layer 806 a and theepitaxy substrate 800 and then removing the dielectric thin film locatedon a top surface of the nitride semiconductor pillar layer 806 a, Here,the mask layer 818 can be made of a dielectric material, such as siliconoxide or silicon nitride.

Next, referring to FIG. 8H, an ELOG process is performed by using thenitride semiconductor pillar layer 806 a as a seed so as to form anitride semiconductor layer 820 such that fifth hollow structures 814′and sixth hollow structures 816′ shown in FIG. 8H are formed. Thenitride semiconductor layer 820 is made of gallium nitride (GaN),aluminum nitride (AlN), indium nitride (InN), gallium indium nitride(GaInN), aluminum gallium nitride (AlGaN), or aluminum gallium indiumnitride (AlGaInN), for example. Based on actual demands, the ELOGprocess is, for example, an HVPE process, an MOVPE process, or an MBEprocess.

If the thickness of the nitride semiconductor layer 820 is equal to orgreater than 50 μm, a cooling process can be selectively performed forreleasing shear stresses caused by difference in thermal expansioncoefficients of epitaxy materials in the nitride semiconductor layer820. Thereby, the interface (the weakest section, e.g. the nitridesemiconductor layer 820) is automatically separated from the nitridesemiconductor pillar layer 806 a, as indicated in FIG. 8I.

In light of the foregoing, the interface between the nitridesemiconductor layer and the substrate is formed by two layers ofpatterned arranged pillars in different sizes according to thedisclosure. Besides, the width of the cross-section of each of thesecond pillars near the nitride semiconductor layer is smaller than thewidth of the cross-section of each of the first pillars near thesubstrate, and the distance among each of the second pillars is greaterthan the distance among each of the first pillars. As such, the contactpoint between the GaN semiconductor layer and each of the second pillarsis weakened and no longer able to withstand stresses, and the contactpoint is cracked to separate the GaN semiconductor layer from thesubstrate. In addition, when the nitride semiconductor thin film isapplied according to the disclosure, the small cross-section of each ofthe second pillars gives rise to a reduction of both dislocation of theepitaxy layer (i.e. the nitride semiconductor layer) and damages tolight-emitting efficiency of the GaN semiconductor layer when the ELOGprocess is performed on the nitride semiconductor layer. Here, thedamages to the light-emitting efficiency of the GaN semiconductor layerare caused by thermal stresses. Moreover, according to anotherembodiment of the disclosure, the nitride semiconductor pillar layercontaining a plurality of first patterned arranged hollow structure anda plurality of nano-sized second hollow structures. Thereby, the nitridesemiconductor thin film can be grown by performing an ELOG process onthe nitride semiconductor pillar layer, and dislocation of the epitaxylayer can be reduced. Additionally, the first and the second hollowstructures are conducive to release of material stresses and thermalstresses, such that cracks of the nitride semiconductor layer anddamages to the light-emitting efficiency of the nitride semiconductorlayer can be both prevented. In case that the nitride semiconductorthick film is grown according to the disclosure, not only thedislocation of the epitaxy layer can be reduced, but also the patternednitride semiconductor pillar layer can be automatically separated in thecooling process. Namely, the shear stresses caused by the difference inthermal expansion coefficients of epitaxy materials are released, andthereby the weakest interface is automatically cracked. As such, afreestanding nitride semiconductor substrate is formed.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of thedisclosure without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the disclosure covermodifications and variations of this invention provided they fall withinthe scope of the following claims and their equivalents.

1. A nitride semiconductor substrate, comprising: an epitaxy substrate;a patterned nitride semiconductor pillar layer formed on the epitaxysubstrate; a nitride semiconductor layer formed on the nitridesemiconductor pillar layer; and a mask layer covering surfaces of thenitride semiconductor pillar layer and the epitaxy substrate, whereinthe nitride semiconductor pillar layer comprises: a plurality of firstpatterned arranged hollow structures; and a plurality of secondpatterned arranged hollow structures located among the first patternedarranged hollow structures, the second patterned arranged hollowstructures having nano dimensions.
 2. The nitride semiconductorsubstrate as claimed in claim 1, wherein a material of the nitridesemiconductor layer comprises gallium nitride, aluminum nitride, indiumnitride, gallium indium nitride, aluminum gallium nitride, or aluminumgallium indium nitride.
 3. The nitride semiconductor substrate asclaimed in claim 1, wherein a height of the first patterned arrangedhollow structures ranges from 1 μm to 10 μm.
 4. The nitridesemiconductor substrate as claimed in claim 1, wherein a width of thesecond patterned arranged hollow structures ranges from 30 nm to 500 nm.5. The nitride semiconductor substrate as claimed in claim 1, wherein aratio of a distance among each of the first patterned arranged hollowstructures to a width of each of the first patterned arranged hollowstructures is more than or equal to 0.5.
 6. The nitride semiconductorsubstrate as claimed in claim 1, wherein a material of the firstpatterned arranged pillars and the second patterned arranged pillarscomprises a III-nitride.
 7. The nitride semiconductor substrate asclaimed in claim 6, wherein the III-nitride comprises nitride of boron,aluminum, gallium, indium, thallium or combination thereof.
 8. Thenitride semiconductor substrate as claimed in claim 1, wherein amaterial of the epitaxy substrate comprises sapphire, silicon carbide,silicon, or gallium arsenide.
 9. The nitride semiconductor substrate asclaimed in claim 1, wherein the first patterned arranged hollowstructures are cyclically arranged.
 10. The nitride semiconductorsubstrate as claimed in claim 1, wherein the second patterned arrangedhollow structures are regularly or randomly arranged.
 11. The nitridesemiconductor substrate as claimed in claim 1, wherein the firstpatterned arranged hollow structures have a stripe-shaped arrangement, adot-shaped arrangement, or a meshed arrangement.
 12. The nitridesemiconductor substrate as claimed in claim 1, wherein a material of themask layer comprises a dielectric material.
 13. The nitridesemiconductor substrate as claimed in claim 1, wherein a nitridesemiconductor freestanding substrate is formed by performing aseparation process on the nitride semiconductor substrate when athickness of the nitride semiconductor layer is more than 50 μm.